This invention relates to a technique for obtaining carrier phase and symbol timing synchronization in a data transmission system, and more particularly to such a technique which is especially useful in data transmission systems operated in the burst mode.
In conventional data transmission systems, for example satellite communications systems, information is transmitted in the form of modulated waveforms, and in order to obtain the transmitted information it is necessary to demodulate the received transmission using a coherent carrier reference signal and a clock signal which is synchronized to the symbol timing of the modulated waveform. The carrier and clock synchronization have conventionally been secured in a number of ways, some of the techniques performing the two synchronizations serially with separate time intervals for each, and some performing the synchronizations in parallel.
A typical series-type carrier and clock recovery system may include a phase-lock-loop (PLL) for the carrier recovery as shown in FIG. 1, and either a differentiation, rectification and phase-lock loop (DRPLL) or digital bit timing recovery (DBTR) for the clock recovery as shown in FIGS. 2 and 3, respectively. In the carrier recovery circuit of FIG. 1, the modulated waveform is supplied to input terminal 10 from which it is supplied as an input to each of mixers 12 and 14. The input signals are then translated to baseband using carrier signals received through a phase-shift circuit 16 from a voltage controlled oscillator (VCO) 18. The output of mixer 12 is supplied to a low pass filter 20 and the data of the output of filter 20 is supplied to the input of comparator 22. Likewise, the output from mixer 14 is supplied through a data filter 26 to the comparator 28.
The data from opposite channels are multiplied in mixers 24 and 30, respectively, and the mixer outputs are differenced in subtractor circuit 32, the output of which is supplied through a loop filter 34 as the control voltage to the VCO 18.
After establishment of a coherent carrier in the carrier recovery circuit of FIG. 1, the data stream can be removed from the received signal and supplied to the input of differentiation circuit 40 in FIG. 2. The differentiated signal is then rectified in rectification circuit 42 and provided as one input to mixer 44 where it is mixed with the output from VCO 46. The mixer output is provided through the loop filter 48 to the voltage control input terminal of VCO 46.
In transmission systems operated in the burst mode, the carrier phase and symbol timing synchronization must be repeatedly derived from each received burst. Thus, a certain amount of "overhead", or surplus signal containing no data, is typically included at the beginning of the burst in order to provide the receiver with sufficient time to derive the carrier phase and symbol timing synchronization prior to receiving the modulated data waveforms. Since the inclusion of this overhead in the burst will necessarily decrease the amount of data which can be included in any given burst, it is desirable to keep the amount of overhead to an absolute minimum. Therefore, the carrier and clock synchronization techniques which are performed in series with separate time intervals for each synchronization are considered undesirable since an excessive amount of time is required for the two synchronizations to be achieved.
Due to the excessive overhead required when series-type carrier and clock synchronization techniques are used in burst-mode data transmission systems, it has been considered generally preferable to employ parallel-type systems in which the two synchronization operations are performed substantially simultaneously. For example, in the remodulation technique of FIG. 3, the received modulated waveform is supplied in parallel to mixers 50 and 52 where it is converted to baseband by in phase and quadrature carriers from phase-shift circuit 54. Bit detectors 56 and 58 are used to provide data bit streams to mixers 60 and 62, respectively. The received waveform is split into in phase and quadrature components in phase shifter 64, and the two components are supplied as the other inputs to mixers 60 and 62. Accordingly, the received waveform is "remodulated" with the data from detectors 56 and 58 to effectively remove the data, and the two remodulated waveforms are then combined in summation circuit 66. The output of summation circuit 66 is provided through a bandpass filter 68 to threshold comparator 70, and the carrier present at the output of threshold detector 70 is supplied back to the phase shift circuitry 54.
In the "X4" carrier recovery circuit of FIG. 4, the received signal is supplied to a fourth-power circuit 80, the output of which includes a component at four times the carrier frequency f. The output of fourth-power circuit 80 is supplied through a band pass filter 82 to a threshold comparator 84, the output of threshold comparator 84 being a digital signal at four times the carrier frequency. This signal is then supplied through a divide-by-four circuit 86 to obtain a coherent carrier.
In a parallel-type carrier and clock synchronization technique, both the carrier and clock must be derived from the received signal, as opposed to the series-type systems in which the carrier is derived from the received signal and is then used to isolate the data from which the clock signal is generated. Accordingly, in FIG. 5, the received signal is supplied directly to one input of mixer 90 and to the other input of mixer 90 through a delay of T/2, where T=1/R, and R is the symbol rate. The output of mixer 92 is provided through a bandpass filter 94 to a threshold detector 96, the output of which constitutes the recovered clock.
Two primary criteria for judging the performance of any synchronization technique are the acquistion speed and steady state performance. As described above, the acquisition speed of series-type carrier and clock synchronization techniques have generally been considered unacceptable for data transmission systems operated in the burst mode. For a number of additional reasons, none of the above-described parallel-type synchronization techniques have proven entirely satisfactory. Concerning the X4 network shown in FIG. 4, the fourth-power circuit 80 results in an inherent loss of 12 dB in S/N. As a result, its mean acquisition time, steady state phase jitter and error rate performance are correspondingly degraded.
In a manner analogous to the X4 carrier recovery technique, the clock synchronization circuitry of FIG. 5 in which clock synchronization is obtained through half symbol delay and squaring also results in an inherent decrease in the S/N, with corresponding decreases in performance.
For carrier recovery alone, the remodulation network shown in FIG. 3 has shown the best overall performance to date, but its feedback structure does not utilize the best estimates possible to remove the data modulation from the carrier. In particular, during the synchronization period, or preamble, the data sequence is known and need not be estimated, whereas the remodulation technique of FIG. 3 utilizes bit detectors 56 and 58 to provide estimated bit streams to the remodulation mixers 60 and 62.
In addition, in all of these techniques, the noise present in the received signal is aggravated by non-linear signal processing, making it more difficult to obtain stable carrier and clock estimates.
A further deficiency of the above-described systems is that burst mode control signals such as acquisition detection, loss of lock and end of burst, which possess a minimum degree of uncertainty, are not readily derived from these structures.